1. Field of the Invention
The present invention relates to a read/verify circuit for multilevel memory cells with ramp read voltage and to a read/verify method thereof.
2. Discussion of the Related Art
As is known, the need to increase the capacity of non-volatile memories has led to the fabrication of multilevel memories, in which each cell is able to store more than one bit. The information, stored as an amount of charge in a floating-gate region, is encoded by fractioning the entrapped charge and, consequently, the threshold voltage. In this way, the characteristic of a multilevel cell is described by a number of curves representing the drain current as a function of the gate voltage and associated each to a different logic value. The result obtainable in terms of storage density is obviously better, the higher the number of levels of each cell.
At the same time, the development of techniques of fabrication of semiconductors, in particular the increase in lithographic precision, has enabled a considerable reduction in the dimensions of the individual cells and has made it possible for increasingly compact devices to be obtained.
The further increase in the storage density in non-volatile memories meets, however, with a limit in the precision required in particular for the read/verify circuits, which are traditionally based upon current comparison. In fact, the increase in the number of levels and the decrease in the gain of the cells caused by the reduction of the dimensions require discriminating currents that are increasingly closer to one another.
Recently, read/verify circuits with ramp read voltage have been proposed. In practice, the same ramp read voltage is supplied simultaneously to the gate terminals of a cell selected in a memory array and of a plurality of reference cells. The reference cells have been previously programmed so as to have intermediate threshold voltages between the possible threshold voltages envisaged for the array cells. As the read voltage increases, the reference cells are turned on in sequence; also the selected array cell is activated, but its turning-on is staggered with respect to the reference cells. In subsequent turning-on instants, then, the reference cells and the array cell start conducting the same reference current, which is injected through a plurality of respective current-mirror circuits. The passage of the current through each cell, whether an array cell or a reference cell, is detected by a respective operational amplifier, which compares the voltage on the drain terminal of the cell itself with a reference voltage. As the read voltage increases, the operational amplifiers associated to the reference cells switch in sequence, and the switching is stored in an appropriate register, which is incremented. When, instead, the operational amplifier associated with the memory cell switches, the register is “frozen” and is no longer modified until there is a reset command for a new read/verify cycle. In practice, the final configuration of the register indicates the relative position of the voltage threshold of the array cell with respect to the threshold voltages of the reference cells and consequently corresponds to the data stored.
The read/verify circuits with ramp read voltage, albeit presenting advantages as compared to the current comparison circuits, suffer from some limitations, due principally to the presence of operational amplifiers and of current-mirror circuits. Operational amplifiers, in fact, are complex and cumbersome, have high power consumption and, moreover, tend to introduce offsets that limit the maximum obtainable precision. Consequently, also the number of levels that can be discriminated is not optimal. Current mirrors, instead, are sensitive to the fluctuations of the supply voltage and can thus easily introduce read errors when the levels of the threshold voltage are close to one another.